1. Field of the Invention
Embodiments of the invention relate to a semiconductor device and a method of manufacturing the semiconductor device. In particular, embodiments of the invention relate to a multi-level transistor and a method of manufacturing the multi-level transistor.
This application claims priority to Korean Patent Application No. 10-2005-0075247, filed on Aug. 17, 2005, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
As semiconductor devices have become more highly integrated, transistor channel lengths have been reduced. Physically reduced channel lengths are known to be related to several problems, including the so-called “short channel effect,” minute pattern formation difficulties, and limitations on constituent semiconductor device operating speed. Additionally, an increase in the potential of an electric field near the drain region of a semiconductor device with a relatively short channel length may generate a so-called “punch-through” causing a related drain depletion region to intrude into a potential barrier around a source region. Additionally, thermo-electron emissions impacting a short channel region may incite avalanche breakdown. Further, a vertically disposed electric field across the short channel region may decrease the mobility of channel carriers. The short channel effect noted above typically increases the current level of the constituent transistor when it is OFF, which in turn degrades a refresh characteristic of a memory device incorporating the transistor.
Therefore, a multi-level transistor having an active region comprising at least two levels has been proposed as a solution to the problems described above. In the multi-level transistor, the active region is disposed in three-dimensions, thereby solving some of the problems associated with transistors having physically reduced channel lengths.
FIGS. 1 through 3 are cross-sectional views illustrating a conventional multi-level transistor.
Referring to FIG. 1, a recessed region 14 is formed in a substrate 10, e.g., a silicon substrate, to define a first active region 12. Then, a first transistor 18 is formed on first active region 12. A first insulating layer 16 is then formed covering recessed region 14 and first transistor 18. Next, a contact hole 20 that penetrates through first insulating layer 16 and exposes first active region 12 is formed.
Referring to FIG. 2, amorphous silicon 22 is formed on first insulating layer 16 and fills contact hole 20. A first portion of amorphous silicon 22 disposed on first insulating layer 16 is then patterned to have a defined length. Next, the first portion of amorphous silicon 22 is annealed, then transformed into crystalline silicon to form a second active region 24. Referring to FIG. 3, a second transistor 26 is then formed on second active region 24.
In the conventional multi-level transistor, the first portion of amorphous silicon 22 is crystallized and then used as second active region 24. That is, annealing is performed on the first portion of amorphous silicon 22 and becomes second active region 24 comprising crystalline silicon. However, although the annealing process is precisely controlled, the first portion of amorphous silicon 22 is not completely crystallized, but remains partially unchanged. Thus, less than the entire surface of second active region 24 is evenly crystallized. This uneven crystallization prevents second active region 24 from having the desired single-crystalline characteristic.